This interactive tool measures the impact of changing the thermal conductivity of the DRAM dielectric on the thermal resistance of the HBM stack. From this one can compute the highest thermally limited DRAM stack height (anything above 20 is impractical for next-gen technologies due to other limitations). This demonstrates how new dielectrics can enable this new stack height. The numbers below can be modified. This model is based on “Breaking Thermal Bottleneck in 3Dz HBM-on-GPU Integration via System-Technology Co-Optimization,” 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1–4, doi: 10.1109/IEDM50572.2025.11353711.
Current total R
113.9
12-high · BEOL 1×
vs baseline 113.9
±0%
no change
Theoretical max stack
12-high
1.0× the baseline stack, within budget
Fig. 01 — Thermal resistance by layer groupLower is better