Interfacial Electrical Properties from Processing History

Predict how industrially relevant semiconductor interfaces form, evolve and acquire their electrical properties from the fabrication history: growth, cooling and annealing.

Problem 02OpenUpdated Nov 2026

SemiconductorsInterfacesProcess modeling

Written with inputs from

Prof. Tibor GrasserProfessor, TU Wien
Prof. Theresia KnoblochAssistant Professor, TU Wien
Prof. Peter SchindlerAssistant Professor of Mechanical and Industrial Engineering, Northeastern University

Si/SiO₂: Ubiquitous, Yet Hard to Predict

Si/SiO₂ interfaces are in all Si electronics, and the industry has built extremely strong manufacturing pipelines to produce high-quality interfaces. Yet turning a fabrication recipe into a clear prediction of the electrical quality of those interfaces still eludes us.

New architectures such as complementary field-effect transistors (CFETs) and gate-all-around FETs (GAAFETs) bring new geometries, orientations and thermal histories to this interface. This requires us to learn the manufacturing pipelines for these new architectures from scratch. Can we build a predictive framework that connects the process history to the final interface quality?

O₂ crosses the surface (F₁), diffuses through the amorphous SiO₂ (F₂) and reacts at the Si/SiO₂ interface (F₃).

The problem

Build a computationally tractable framework that predicts how semiconductor interfaces form, evolve and acquire their electrical properties from fabrication history.

Given the starting materials, geometry, orientation, composition, doping and surface preparation, together with the temperature and ambient history, predict layer thicknesses, composition profiles and the resulting electrical quality after growth, cooling and annealing.

Target properties to predict from process history

Layer thicknessesOxide, interlayer, consumed substrate
Composition profilesC(z) across the interface
Electrical qualityInterface-trap density D_it(E) and fixed oxide charge Q_f

Five interfaces to validate on

The same framework must carry, unchanged in form, across all five.

Planar Si/SiO₂

Oxide thickness, energy-resolved interface-trap density D_it(E), and fixed oxide charge Q_f versus orientation, oxidation history and hydrogen passivation.

Reference to reproduce: Vitkavage, Irene and Massoud, Journal of Applied Physics 68, 5262 (1990).

Si nanowires and nanosheets

Oxide profile, remaining silicon dimensions, stress-dependent growth slowdown or self-limitation, and D_it(E) and Q_f at the resulting interface.

Reference to reproduce: Kao et al., IEEE Transactions on Electron Devices 35, 25 (1988).

SiC/SiO₂

Face-dependent growth kinetics and temperature dependence, accounting for carbon removal, together with D_it(E) and Q_f after oxidation and passivation.

Reference to reproduce: Song et al., Journal of Applied Physics 95, 4953 (2004).

HfO₂/SiO₂/Si gate stack

Interfacial SiO₂ regrowth versus annealing history, and the evolution of traps and charge. Oxygen exchange and transport must be considered.

Reference to reproduce: Goncharova et al., Physical Review B 83, 115329 (2011).

Ge/GeO₂ and SiGe/oxide

Oxide growth or loss, Ge enrichment and composition profiles, and the resulting D_it(E) and Q_f. Account for GeO desorption, selective oxidation and the appropriate transport mechanism.

References to reproduce: Wang et al., Applied Physics Letters 111, 052101 (2017) for Ge and Rabie, Haddara and Carette, Journal of Applied Physics 98, 074904 (2005) for SiGe.

Submissions

We evaluate submissions on their ability to reproduce accepted literature results that we collate. The first such dataset is Vitkavage, Irene and Massoud, Journal of Applied Physics 68, 5262 (1990): oxide thickness, interface-trap density D_it(E) and fixed oxide charge Q_f on thermally oxidized (100), (110), (111) and (511) silicon, as they vary with oxidation history and hydrogen passivation.

We then check the model on the other four interfaces (Si nanowires and nanosheets; SiC/SiO₂; the HfO₂/SiO₂/Si gate stack; Ge/GeO₂ and SiGe/oxide) against measured thicknesses, composition profiles and electrical data.

Submissions should include:

Method: A description of the proposed computational approach and its underlying scientific principles.
Implementation: Working code and instructions that take the starting process history and compute the electrical properties. Empirical parameters are allowed; if they were fit to a particular chamber or tool, say so.

Because results vary from tool to tool, we assess submissions qualitatively first, for example whether a hydrogen anneal reduces D_it, and then quantitatively. For extremely promising models we also run in-house experiments to validate the predictions.

Evaluation considers:

Predictive accuracy: Agreement with the measured thicknesses, composition profiles and electrical data.
Transferability: One framework, with declared parameters, across all five interfaces.
Reproducibility: The ability to run the code from a stated process history and recover the reported results.

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